1. Field of the Invention
The present invention relates to semiconductor device having a memory cell portion and manufacturing method thereof, and more particularly, to a semiconductor device directed to lowering of the resistance of the connection portion of a field effect transistor and a manufacturing method thereof.
2. Description of the Related Art
Semiconductor devices using a MOS (Metal Oxide Semiconductor) field effect transistor have been developed in various fields and implemented as a device having multiple functions as the technique of reducing the size and the technique of high density integration have advanced. As a typical semiconductor device having multiple functions, a semiconductor device including both a DRAM (Dynamic Random Access Memory) and a logic is known. Disadvantages associated with the multiple function semiconductor device will be now described.
FIGS. 1A and 1B are cross sectional views showing the memory cell portion and peripheral circuit portion of a conventional DRAM. As shown in FIGS. 1A and 1B, in the peripheral circuit portion, a MOS transistor having an n type diffusion layer and a p type diffusion layer is formed. As shown in FIG. 1A, a p well 242 is formed on the surface of a semiconductor substrate 241, and a plurality of element isolation oxide films 243 are formed on the surface of the p well 242. Thus, a memory cell portion 260 and a peripheral circuit portion 270 are partitioned and there are a plurality of element regions in the memory cell portion 260 and the peripheral circuit portion 270. At the surface of the p Well 242 in an element region in the memory cell portion 260, an n type diffusion layer 244 is formed. At the surface of the p well 242 in an element region in the peripheral circuit portion 270, an n type diffusion layer 274 is formed. The n type diffusion layer 274 in the peripheral circuit portion 270 is formed to a position deeper than the n type diffusion layer 244 in the memory cell portion 260. An interlayer insulating film 246 is formed at the upper surfaces of these element regions. In the interlayer insulating film 246, there is a memory cell portion contact 247 connected to the n type diffusion layer 244 and filled with a phosphorus-doped polysilicon plug 250 formed of a phosphorus-doped polysilicon film. Also in the interlayer insulating film 246, there is a peripheral circuit portion contact 248 connected to the n type diffusion layer 274 in the peripheral circuit portion 270, and a phosphorus-doped polysilicon plug 251 formed in the same process is filled therein. A metal interconnection 255 connected to these phosphorus-doped polysilicon plugs 250 and 251 is also formed.
In FIG. 1B, a p type diffusion layer 245 is formed on the surface of the p well 242 in the peripheral circuit portion 270. An interlayer insulating film 266 is formed on the interlayer insulating film 246 and the metal interconnection 255. A peripheral circuit portion contact 258 reaching the p type diffusion layer 245 is formed in the interlayer insulating films 266 and 246, and a metal plug 254 is filled therein. A metal plug 256 connected to the metal interconnection 255 is formed in the interlayer insulating film 266. Similarly to FIG. 1A, in the memory cell portion 260, a phosphorus-doped polysilicon plug 250 is filled in the memory cell contact portion 247 provided in the interlayer insulating film 246, and is connected to the n type diffusion layer 244.
The phosphorus-doped polysilicon plug 250 normally has the same conductivity type as that of the n type diffusion layer 244. As a result, when an n type polysilicon plug of the same conductivity type as the polysilicon plug in the memory cell portion 260 is formed in the peripheral circuit portion contact 258 on the p type diffusion layer 245 in the peripheral circuit portion 270, a pn junction forms and application of a voltage across the region between the n type polysilicon plug and the p type diffusion layer causes an undesirable rectifying effect therebetween. Therefore, an n type polysilicon plug cannot be used for the peripheral circuit portion contact 258, and a metal plug is used instead. Thus, the p type diffusion layer 245 in the peripheral circuit portion is connected to the upper metal film interconnection 265 through the metal plug 254 filling the peripheral circuit portion contact 258 and then connected to the metal interconnection 255 through the metal plug 256 provided in the interlayer insulating film 266.
Note however that as the size of a memory cell portion contact is reduced with reduction in the size of elements, the resistance of the n type polysilicon plug increases, which could cause a fault in the operation of cells. A metal plug may be used instead of the n type polysilicon plug for the contact of the memory cell portion, but the use of the metal plug increases diffusion layer leakage. As a result, a metal plug cannot be used for forming the memory cell portion contact unlike for the peripheral circuit portion contact.
It is an object of the present invention to provide a multifunction semiconductor device including memory cells with a reduced size, having a low resistance contact plug without diffusion layer leakage in the memory cell portion and a low resistance contact plug in the peripheral circuit portion of the memory cell portion.
A semiconductor device according to a first aspect of the present invention includes: semiconductor substrate; an element formed on said substrate; an interlayer insulating film formed on said semiconductor substrate; a first opening provided in said interlayer insulating film and reaching the surface of said semiconductor substrate; a second opening having a larger opening size than the first opening; a first plug having a lower conductive silicon film filled within a lower portion of said first opening and a metal film filled within an upper portion of said first opening; and a conductive, second plug filled within said second opening.
A semiconductor device according to a second aspect of the present invention includes: a semiconductor substrate; an element formed on said substrate; a gate insulating film formed on said semiconductor substrate; first and second gate electrodes formed on said gate insulating film; a sidewall insulating film formed on a sidewall of said gate electrode; an interlayer insulating film covering an upper surface of said semiconductor substrate including said gate electrode and said sidewall insulating film; first and second openings provided in said interlayer insulating film and reaching the surface of said semiconductor substrate; and conductive, first and second plugs filled within said first and second openings, respectively, said first gate electrode being formed at a first interval smaller than twice the thickness of said sidewall insulating film, and said second gate electrode being formed at a second interval larger than twice the thickness of said sidewall insulating film.
In the semiconductor devices according to the first and second aspect of the present invention, the first plug has a conductive silicon film filled within a lower layer portion of the first opening and the plug upper layer metal film filled within an upper layer and the second plug has conductive film filled within the second opening and can be directly connected to a diffusion layer. Therefore, the resistance of second plug reduced. In addition the device will not degrade the leakage characteristic in the first plug formed in a memory cell.
A method of manufacturing the semiconductor device according to a first aspect of the present invention includes the steps of: forming first and second diffusion layers on a surface of a semiconductor substrate; forming an interlayer insulating film on said semiconductor substrate including said first and second diffusion layers; forming first and second openings in a region of the interlayer insulating film on said first diffusion layer and a region of the interlayer insulating film on said second diffusion layer, respectively to expose surfaces of said first and second diffusion layers; depositing a conductive silicon film on said semiconductor substrate; etching back said conductive silicon film to form a lower portion of a first plug in a lower portion of said first opening while at the same time removing the conductive silicon film at the bottom of said second opening to expose a surface of said second diffusion layer; and depositing a metal film on said semiconductor substrate including said first and second openings, filling said first and second openings with said metal film to form an upper portion of said first plug on said lower conductive silicon plug in said first opening while at the time forming a second plug by said metal film filling within said second opening with the sidewall conductive silicon film.
A method of manufacturing the semiconductor device according to a second aspect of the present invention includes the steps of: forming first and second diffusion layers on a surface of a semiconductor substrate; forming an interlayer insulating film on said semiconductor substrate including said first and second diffusion layers; forming a first opening in a region of the interlayer insulating film on said first diffusion layer to expose a surface of said first diffusion layer; depositing a conductive silicon film to fill a lower portion of said first opening with said conductive silicon film, thereby forming a lower portion of a first plug; depositing an upper metal film to fill an upper portion of said first opening with said upper metal film, thereby forming an upper portion of said first plug; forming a second opening in a region of the interlayer insulating film on said second diffusion layer to expose a surface of said second diffusion layer; and depositing a metal film on said semiconductor substrate including said second opening to fill said second opening with said metal film, thereby forming a second plug.
A method of manufacturing the semiconductor device according to a third aspect of the present invention includes the steps of: forming first and second diffusion layers on a surface of a semiconductor substrate; forming an interlayer insulating film on said semiconductor substrate including said first and second diffusion layers; forming first and second openings in a regions in the interlayer insulating film on said first and second diffusion layers, respectively and exposing only a surface of said first diffusion layer; depositing a conductive silicon film to fill a lower portion of said first opening with the conductive silicon film, thereby forming a lower portion of a first plug; exposing a surface of said second diffusion layer at the bottom of said second opening; and depositing a metal film on said semiconductor substrate including said first and second openings, filling an upper portion of said first opening with said metal film to form an upper portion of said first plug, while at the same time filling said second opening with said metal film to form a second plug.
A method of manufacturing the semiconductor device according to a fourth aspect of the present invention includes the steps of: forming first and second gate electrodes on a semiconductor substrate, the distance between said first gate electrodes being narrow than the distance between said second gate electrodes; forming a first sidewall insulating film at sidewalls of said first and second gate electrodes; forming a first diffusion layer on said semiconductor substrate using said first gate electrode and said first sidewall insulating film as a mask and forming a second diffusion layer on said semiconductor substrate using said second gate electrode and said first sidewall insulating film as a mask; forming a second sidewall insulating film on said first sidewall insulating film; depositing an etching stopper film; forming an interlayer insulating film on said etching stopper film; etching said interlayer insulating film, said etching stopper film and said first and second sidewall insulating film so as to form a first opening in a region on said first diffusion layer exposing a surface of said first diffusion layer and a second opening in a region on said second diffusion layer exposing said etching stopper film; depositing a conductive silicon film to fill a lower portion of said first opening with the conductive silicon film, thereby forming a lower portion of a first plug; removing said etching stopper film at the bottom of said second opening to expose a surface of said second diffusion layer; and depositing a metal film on said semiconductor substrate including said first and second openings, filling an upper portion of said first opening with said metal film to form an upper portion of said first plug in said first opening while at the same time filling said second opening with said metal film to form a second plug in said second opening.
In the methods of manufacturing the semiconductor device according to the first to fourth aspect of the present invention, the conductive silicon film is any of a polysilicon film, an amorphous silicon film, an epitaxial layer, and a silicon-germanium compound crystal. If the conductive silicon film is an amorphous silicon film, the amorphous silicon film may be reformed into a polysilicon film after the first and second openings are filled with the metal film.
The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals or characters.